In many computing systems today, memory (e.g., Random Access Memory) stores data to be used by the processor in computing instructions. For example, memory may store two operands to be added by a processor and store the result from the summation of the two operands. Thus, in the example, the processor may access the memory to read the two operands and again access the memory to write the result.
Memory may have a slower operating speed than the processor. Therefore, the processor may wait during an access of the memory. Hence, power and time is consumed by the computing device while the processor may be idle waiting for access of the memory. To increase the overall processing speed and reduce power consumption of the computing system, a cache with a faster operating speed than the memory may be coupled to the processor. The cache includes a plurality of cache lines, wherein each cache line may store a portion of the data in memory.
Since the cache is faster than the memory, data that may be used by the processor is preloaded into portions (e.g., cache lines) of the cache. Hence, when the processor is to retrieve data for processing, the processor accesses the cache for the data. If the cache does not include the data, the memory is accessed for the data.
As more data is preloaded into the cache, previously stored data may be replaced with newly computed or retrieved data. As a result, a system may exist that is configured to determine the sequence that cache lines are to be populated and/or replaced. In conventional processors, the cache lines of the cache are used in sequence, wherein the processor loops back to the first cache line once reaching the last cache line of the cache. A system may exist in the processor to determine and point to the next cache line to be used by the processor. One such system implements a First In First Out (FIFO) cache replacement policy, wherein pointers are incremented in order to sequentially point to the next cache line of the cache.
A program may be executed by a processor to include cache maintenance instructions to invalidate a cache line. Since instructions may invalidate cache lines, invalid cache lines may exist in the cache while the system points to a valid cache line to be replaced by the processor. As a result, in a cache implementing a FIFO replacement policy, a valid cache line may be replaced by a load operation while an invalid cache line exists. One problem in this approach is that a decrease in valid cache lines may require the processor to more frequently access the memory, thus causing an increase in power consumption and a decrease in computing speed.